Quartus II 13.1 (upgraded) fails terribly where Xilinx produces perfect RTL schematics from the same VHDL code! And I already upgraded Quartus to get rid of the wrong terrible bugs that showed in its RTL results.And I think it is caused by differences in the FPGA structures and/or differences between the VHDL designers from Quartus and Xilinx: I did however leave another answer on the Forum that was another problem. Hi KhaiY, this problem was already solved in the past by upgrading my buggy 13.1 Quartus II version.
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